Packaged semiconductor dies, including memory dies, microprocessor dies, and interface dies, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry, as well as bond pads electrically connected to the functional features. The bond pads are often electrically connected to external terminals that extend outside of the protective covering to allow the die to be connected to busses, circuits or other higher level circuitry.
Semiconductor die manufacturers are under increasing pressure to continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. Stacking multiple dies, however, increases the vertical profile of the device, requiring the individual dies to be thinned substantially to achieve a vertically compact size. Additionally, the stacking of multiple dies can increase the probability of device failure, and lead to higher costs associated with longer manufacturing and testing times.
FIG. 1 illustrates a conventional system 10 including multiple semiconductor stacked assemblies. As shown, the system 10 includes printed circuit boards (PCBs) 15 arranged in dual in-line memory module (DIMM) slots and separated from one another by a given center-line to center-line pitch (i.e., ˜7.6 mm). Semiconductor packages 12 are attached to each of the PCBs 15 in a stacked arrangement. Specifically, bottom portions of each semiconductor package 12 are attached via solder balls 13 to opposite sides of the PCBs 15. The conventional system 10 has limited space between the semiconductor packages 12 (i.e,  1 mm) on adjacent DIMM slots, which can limit airflow therebetween required for thermal control and restrict the performance of the packages. Accordingly, there is a need for other approaches to providing semiconductor devices with smaller footprints, while still maintaining sufficient functional capacity to meet operating parameters.